Design of FIR Filter using Distributed Arithmetic Architecture
نویسندگان
چکیده
--Digital filters can be realized in hardware, software. In general digital filters tend to be more expensive than analog filters.But digital filters can be used to implement complex applications that analog filters cannot. This paper presents the design of a double-precision lowpass direct form Finite Impulse Response (FIR) filter to meet the given specification. Simulation results have been presented. Keywords---Distributed Arithmetic, Double Precision, Finite Impulse Response, HDL, Quantized. __________________________________________________*****_________________________________________________
منابع مشابه
A Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithmetic with Decomposed LUT
Abstract: In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 3-input LUT-based structure of FPGAs. The implementation of FIR filters on FPGA based on traditional arithmetic method costs considerable hardware res...
متن کاملMemory Efficient Architecture For High Speed Fir Filter Using Distributed Arithmetic
This paper presents the realization of memory efficient architecture using Distributed Arithmetic (DA) for implementation of Finite Impulse Response (FIR) filter. Here, the multipliers in FIR filter are replaced with multiplier less DA based technique. First, the theory of DA is described. In this technique, pre-computed values of inner product are stored in LUT, which are further added and shi...
متن کاملDistributed Arithmetic Unit Design for Fir Filter
In this paper different distributed Arithmetic (DA) architectures are proposed for Finite Impulse Response (FIR) filter. FIR filter is the main part of the Digital Signal Processing. In Digital Signal Processing we can use Multiply Accumulator Circuit (MAC) and DA for filter design.MAC consumes more power and area because of multiplier and adder circuit. The design distributed arithmetic is run...
متن کاملDesign and implementation of DDA architecture for FIR Filters
Traditionally, direct implementation of a K-tap FIR filter requires K multiply-and-accumulate (MAC) blocks, which are expensive to implement in FPGA due to logic complexity and resource usage. To resolve this issue, we first present DA, which is a architecture without multiplier. This paper implements the DA architecture. This architecture is applicable to only one type of filter Coefficients i...
متن کاملImplementation of High Speed Pipelined Distributed Arithmetic Based FIR Filter
In the explosive growth of wireless and networking applications, Digital Signal Processing (DSP) operations are extensively used for characterizing and controlling the discrete input signals. For those DSP operations, Finite Impulse Response (FIR) filter is used to filter the unwanted/noise/distorted signals from the discrete input signals. In this study, design of Pipelined Distributed Arithme...
متن کامل